We are looking for a motivated and talented Digital Designer to join our team in creating next-generation Power management solutions. We are looking for a visionary designer to lead the transition from traditional PMICs to Intelligent Power Systems. You will take full ownership of the design cycle, from architecture definition till Tapeout.

Core Responsibilities

• Ownership of Digital Micro architecture : Develop optimized sub-block architectures, translating complex requirements into efficient RTL and gate-level netlists. Create New IP solution distributed between Analog and digital.
• Must have experience of designing complex state machines, Power sequencers, various control loops and data processing modules.
• Lead silicon debug, perform root-cause analysis, and drive design-to-silicon correlation to ensure first-pass success.
• Deep expertise in power-sensitive digital design, power estimation,  CDC ( clock domain crossing), Lint flows.
• Knowledge of OTP, Efuse controllers, various memories controllers.
• Mastery of communication protocol, I2C, SPI, PMBUS, SVI3, and SVID. You are expected to build High speed, low pin count custom Interface solution.
• Should be able to implement and analyse filters & feedback loops in Digital, conversant with Z-domain analysis.
• Proficient with front end flows and RTL coding using Verilog.