Key Responsibilities:

• Own subsystem/block-level floorplanning and end-to-end place-and-route (PnR) flow for low-power, high-performance designs, including debugging of timing, power, and area issues, clock tree analysis, and contributing to full-chip timing convergence and closure.

• Collaborate closely with cross-functional teams, including Design and DFT, to streamline and enhance the PnR flow.

• Drive robust IP integration strategies to ensure high-quality ASIC delivery while minimizing schedule risks.

• Perform in-depth design and timing analysis to identify critical paths and implement effective strategies to mitigate timing violations and improve overall design convergence.

• Stay current with industry trends and emerging technologies in PnR and related domains, and incorporate best practices into team workflows.

• Prepare and present comprehensive technical analyses, reports, and documentation to stakeholders.

• Promote a culture of innovation, collaboration, and continuous improvement within the PnR team