Western Digital

Job description:

Responsibilities:-

• Strong knowledge in IP/SOC design methodologies.
• Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
• Strong experience in Synthesis, timing, full chip netlist & front-end design tools& flows Low power design
• Mentoring juniors and enhancing their skill set
• Expert knowledge on code coverage, functional coverage, Lint, CDC etc
• Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures
• Defining requirements for ASIC design, verification, and physical implementation teams
• Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
• Reviewing and configuring 3rd party IPs
• Supporting other teams in the ASIC organization and reviewing their work
• Supporting product teams with documentation, code-reviews, and silicon debug
• Continuously finding opportunities for improving design quality and design practices

Qualifications
 Bachelor/ Master degree in Electronics/VLSI/Micro-Electronics Engineering