Western Digital

Job Description:-
You should have strong knowledge and experience with all aspects of the SOC design and implementation flow – including datapath design, low power design, clock and reset schemes, coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understanding of how architecture decisions impact these flows. You will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities in our storage-based controllers.

DUTIES AND RESPONSIBILITIES:

• Strong knowledge in IP/SOC design methodologies.
• Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
• Strong experience in Synthesis, timing, full chip netlist & front-end design tools& flows Low power design
• Mentoring juniors and enhancing their skill set
• Expert knowledge on code coverage, functional coverage, Lint, CDC etc
• Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures
• Defining requirements for ASIC design, verification, and physical implementation teams
• Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
• Reviewing and configuring 3rd party IP

Please contact us at staffingsupport@wdc.com