Senior PHP Developer
Nexgen private limited- 6 - 7 yrs
- 54,000 - 64,000 / month
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Full Time
Working Type : Work From Office
Job Description :
Job Description
We are seeking an experienced Senior PHP Developer with strong Magento expertise to join our team. The ideal candidate has solid experience in building and maintaining online stores, a strong understanding of MySQL, and good knowledge of standard PHP development practices. The role focuses on developing, customizing, and optimizing eCommerce solutions.
Working hours: 4 hours overlap with EST
Responsibilities
- Develop, customize, and maintain Magento-based eCommerce websites
- Build and enhance features for online stores, including product management, checkout, payments, and integrations
- Write clean, scalable, and well-documented PHP code
- Design and optimize MySQL databases and queries
- Integrate third-party APIs, payment gateways, and shipping services
- Troubleshoot, debug, and upgrade existing systems
- Optimize application performance and ensure high availability
- Collaborate with designers, front-end developers, and stakeholders to deliver high-quality solutions
GIMU Associate
Nexgen private limited- 2 - 3 yrs
- 24,000 - 36,000 / month
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Full Time
Working Type : Work From Office
Job Description :
To achieve your targets, you will need to understand the various tools and systems used by the Marketing Operations team and establish a firm grasp of them. You will need to work with multiple teams and across all departments and locations.
What you will do
- Monitor live reporting across Propositions, Commercial and Customer Experience
- Provide Operational / CMS support including during non-core business hours
- Handle CS escalations to the Operations team
- Receive the KPI reports, compare to expected behavior and investigate potential issues for the UK&Ire Brands
- Sanity checks the websites of the UK Brands to ensure everything is performing as expected
- Identify and eliminate game technical issues as and when they appear by escalating to the relevant team
- Create, follow up and resolve all related incidents
- Review the causes and resolutions for issues and recommend process / product improvements to prevent them
- Communicate effectively across cross-functional teams
- Work on critical issues around content amendments
Sr StaffStaffSenior Engineer IP Design Verification
Nexgen private limited- 7 - 8 yrs
- 62,000 - 70,000 / month
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Full Time
Working Type : Work From Office
Job Description :
We are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. In this role, you will be a part of team responsible for SOC verification, ensuring first‑pass silicon success through building verification environment from scratch using best in class methodologies, metric‑driven verification, and intelligent coverage convergence using AI tools.
You will play a key technical role in defining verification strategies, architecting testbenches, defining Test Plans tracing Requirements, driving coverage closure using advanced automation and AI‑assisted techniques, and collaborating closely with Architecture, RTL, chip top, and Validation teams to deliver high‑quality, reusable IPs for next‑generation microcontrollers and microprocessors.
Responsibilities:
- Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
- Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
- Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
- Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
- Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
- Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
- Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
- Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
- Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
- Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
- Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
- Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.
- Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.
- 6 - 7 yrs
- 52,000 - 59,000 / month
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Full Time
Working Type : Work From Office
Job Description :
Job Description
Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.
Renesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.
Key Responsibilities
- Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
- Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
- Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
- Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
- Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
- Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
- Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions